SOC Digital Design Engineer

SOC Digital Design Engineer


  • Do the top-level and/or block-level design and simulation

  • Design/implement SOC essential parts including clock/reset generation, power domain related thing, boot, power management block etc

  • Do front-end job covering block-level (and/or top-level) synthesis, timing analysis, CDC check, lint check, formality check etc

  • Do silicon gate-level ECOs

  • Support the block-level and/or top-level verification

  • Support FPGA platform development and FPGA bit file generation


  • Highly motivated and self-directed

  • Good documentation skill

  • Not bad in English

  • Bachelor’s degree or equivalent in Computer Science, Electrical, Electronics Engineering or related field

  • Strong knowledge in SOC architecture from CPU, bus, memory, peripherals, GPIO through clock, reset, power, power domain to boot, sleep/wake-up, interrupt, security

  • 5+ years of experience in SOC digital design (Experience in wireless SOC is a plus)

  • Very strong skills in Verilog RTL coding and simulation (experience on metal layer ECO is a plus)

  • Good understanding on OS/driver (C coding capability is a plus)

  • Hands-on experience in front-end EDA tools, synthesis DC/DCT/DCG, PT etc

  • This field is for validation purposes and should be left unchanged.
  • This field is for validation purposes and should be left unchanged.