Do the top-level and/or block-level and/or IP simulation
Do the block-level and chip-level verification
Develop FPGA platform and do FPGA bit file generation
Verify PCIe inside SOC during SOC chip design phase and during a chip bring-up
Verify USB3.0 inside SOC during SOC chip design phase and during a chip bring-up
Make PCIe and USB verification plan under FPGA test environment and do verification through FPGA test, working together with software engineer and system board engineer
QUALIFICATIONS AND SKILLS
Highly motivated and self-directed
Good inter-personal communication skills
Good documentation skills
Not bad in English
Bachelor’s degree or equivalent in Computer Science, Electrical, Electronics Engineering or related field
3+ years of experience in SOC digital design or verification
Very strong skills in Verilog RTL simulation (RTL coding capability is a plus)
Good understanding on OS/driver and simple C coding capability
Hands-on experience on FPGA bit generation flow including FPGA synthesis and P&R tool