RFIC Layout Design Engineer

RFIC Layout Design Engineer

JOB RESPONSIBILITIES:

  • Work with the RF/Analog/PMU design team to achieve competitive advanced CMOS SoC for WiFi6, Bluetooth/BLE and following WiFi7 application. Responsible for layout design and verification for RF, Analog and PMU modules and top integration
  • Reasonably design the top floorplan of RFIC and PMU sub-blocks according to the requirement of SoC PR and RF/Analog/PMU designers, optimize the layout area without any performance sacrifice
  • Contact Foundry interface for design rules update, help to drive tapeout procedure and chip package design


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