Wi-Fi PHY Developer 2

Wi-Fi PHY Developer 2

Key Requirements:

  • Strong background in FPGA/SoC implementation of digital baseband modem. (best if WLAN).
  • Knowledge and 5+ years of experience in communication systems and physical layer RTL design.
  • Expert level of RTL design(Verilog) skill for implementation and verification of modem algorithms (FFT, LDPC, Viterbi and so on.) from fixed point C/C++ code.
  • Extensive experience of FPGA/ASIC targeted PHY RTL design for area/timing optimization.
  • Ability to fit large-scale & high-speed design into Xilinx FPGA implementation.
  • Understand system-level issues of complex communication systems in real world.
  • Good team player.

Additional Plus:

  • Ability to operate lab equipment.
  • Can implement analog/RF modeling and analog/digital mixed simulation.
  • Experienced co-working with PHY algorithm team.
  • Good understanding of 802.11ac/ax WLAN system Implementation of LDPC encoder/decoder and/or complex matrix decomposition
  • Written English, Spoken and Listening English is plus.

Job description:

  • Development of WLAN PHY RTL design/verification.
  • Analyze C(or C++)-level simulator and build logic implementation architecture.
  • Area/Timing critical block optimization.
  • RTL code optimization and migration for FPGA and ASIC.
  • Study of implementation design method in terms of area.
  • Clock tree design/implementation for baseband.

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  • This field is for validation purposes and should be left unchanged.